基于fpga的dm900a模块

单周期CPU，Verilog源码，                                              解压即可运行。

vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)

本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.(program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.)

Arbiter code for simulation purpose

qsys-niosii-triple-speed-ethernet-3c120-v10-1

Clock Divider, divfactor of 18

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

基于vhdl的pid控制器设计，可以用quartus等软件实现。数字控制系统pid设计源代码。(Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co)

沃尔什函数序列sequency的verilog编程实现，含有测试文件(the Walsh sequence in sequency order)