qsys-niosii-triple-speed-ethernet-3c120-v10-1

the interface design of pcie based on FPGA

German REAL LPT! USB2LPT

用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)

说明：  设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主 机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值， 并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号， 当计数器满足模式配置后的计数要求时，会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB The computer configures the counter through the address and sets the maximum value of the counter through the data input port, And output the count value of the counter through the data output port. The design also sets a count completion signal, When the counter meets the counting requirements after the mode configuration, the signal will be pulled high)

说明：  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

FPGA做VGA视频显示的详细资料，我找了很久才收集起的，有四篇文章，很有用(FPGA do VGA video display detailed information, I found a long time before they start collecting, with four articles, very useful)

通过调用三速以太网IP核，上层实现ARP,TCP,UDP协议，以太网芯片是88E1111，绝对可用，支持千兆以太网，GMII接口。

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

basic cpu design in verilog

快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)