cpu32 _加法器

通过matlab代码对一组输入的字符串进行编码后，通过matlab内置函数对进行编码后的字符串进行哈夫曼树绘制。 通过matlab代码对一组输入的字符串进行编码后，通过matlab内置函数对进行编码后的字符串进行哈夫曼树绘制。

that file is different I2S example

verilog编写，巧妙的通过计数方式完成了三角波的波形，可直接对da输出。(verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.)

這是一般通訊介面會採用的8B/10B 解碼, 應用在光纖通訊, Serdes上均有廣泛應用 /* Module Description:  This module implements a 8b10b decoder according to the original patent work  of Widmer and Franaszek.  It is a synchronous module with registers on the input  and output.  It takes in a 10-bit 8b10b encoded word, and outputs and 8-bit data  word and a control bit to indicate if the 8-bit output data is one of 12 special  K-codes.  */

Time divisor vhdl code

说明：  fpga 静态时序分析 是电子工程中，对数字电路的时序进行计算、预计的工作流程，该流程不需要通过输入激励的方式进行仿真。(Static time series analysis is a work flow which can calculate and predict the time series of digital circuits in electronic engineering.)

spi协议的verilog实现，其中包括4个模块，可以达到很大的测试时钟频率，也已经通过了流片验证，FPGA验证。其中有防抖模块来减少防抖。通过状态机实现，既可以串并转换，可读可写

FIFO is a First-In-First-Out memory queue with control logic that manages  the read and write operations, generates status flags, and provides optional  handshake signals for interfacing with the user logic. It is often used to  control the flow of data between source and destination. FIFO can be  classified as synchronous or asynchronous depending on whether same clock  or different (asynchronous) clocks control the read and write operations. In  this project the objective is to design, verify and synthesize a synchronous  FIFO using binary coded read and write pointers to address the memory  array. FFIO full and empty flags are generated and passed on to source and  destination logics, respectively, to pre-empt any overflow or underflow of  data. In this way data integrity between source and destination is maintained.  The RTL description for the FIFO is

四选一多路选择器,使用Verilog语言实现了多路选择器，可以通过FPGA实现四选一多路选择器，数字逻辑电路的相关内容。欢迎大家下载，使用vivoda打开，烧写在开发板上。

说明：  包括HDMI和DVI的源文件，以及相应打仿真文件(Including HDMI and DVI source files, as well as the corresponding simulation files)