6502原码

说明：  quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

8级cordic 算法verilog (8 cordic algorithm verilog)

以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)