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电压采集系统
FPGA接AD模块通过数码管显示电压数据,将模拟信号转换成数字信号进而通过数码管实时显示电压,相当于一个简易的电压表。
- 2022-06-01 05:05:07下载
- 积分:1
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密码连接器
这是我试图实现键盘的代码,但它有一些错误,我不知道,但如果你有能力使它正确,请纠正它,并再次上传
- 2022-05-19 16:45:55下载
- 积分:1
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基于FPGA和IP核的FIR低通滤波器
用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
- 2017-10-11 10:06:40下载
- 积分:1
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CAN
说明: ZYNQ中 PS 端 CAN接口的基本使用方法,并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
- 2020-04-03 16:41:52下载
- 积分:1
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test_ad9852
使用FPGA来控制DDS信号的产生,从而达到高频信号产生的目的。使用的DDS芯片为AD9852,在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)
- 2010-01-27 17:02:16下载
- 积分:1
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xapp1251
说明: 1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. SUPPORT
- 2020-11-07 09:49:49下载
- 积分:1
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seg7
SEG7数码管显示示例程序,适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分:1
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PID controller verilog源代码
The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).
- 2022-09-23 12:05:03下载
- 积分:1
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VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分:1
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verilogUART
verilog实现的串口实现代码,可以直接复制使用(verilog achieve serial implementation code can be copied directly use)
- 2013-03-19 21:09:23下载
- 积分:1