PID controller verilog源代码

在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)

篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号(basketball 24 seconds)

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// //creat for the zedboard .  //The AD used ADV7511. ////////////////////////////////////////////////////////////////////////////////// module ad( datain , clk , rst , dataout );     input [11:0] datain;     input clk;     input rst;        output [11:0] dataout;

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

键盘计算器，可实现加减乘数运算 基于fpga nios2(Keyboard, calculator, addition and subtraction can be realized based on fpga nios2 multiplier operator)

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)

verilog编写的GPS /BD基带逻辑代码，包含跟踪相关部分代码，有比较好的借鉴意义。

AHB BUS 的一些接口代码， verilog, 希望对初学AHB总线的兄弟有所帮助。 里面包含 ahb decode, ahb_mux and ahb2mem. 以及相应的验证环境， 此代码只用于学习，如果用于项目，仅供参考。

SDR SDRAM 控制器的源代码 altera公司的(source code from altera)

说明：  Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)