电压采集系统

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )

VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)

说明：  有限状态机 rtl code 和 TB验证环境(Finite state machine RTL code and TB verification environment)

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)

verilog实现的串口实现代码，可以直接复制使用(verilog achieve serial implementation code can be copied directly use)

48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)