FPGA中VGA接口

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

该模块已经成功运用在xilinx xc6slx45t，xc6slx75t多个产品中，经过实践证明，采用dna及其加密算法加密是一种成本低廉（无需另外加密芯片）可靠的加密手段。Xilinx Spartan-6 FPGA读取DNA数据并进行比较，产生比较结果信号输出。附带有xilinx DNA.ppt说明及调试注意事项。(The module has been successfully used in xilinx xc6slx45t, multiple xc6slx75t products, proven, and the encryption algorithm uses dna is a low-cost (no additional encryption chip) reliable means of encryption. Xilinx Spartan-6 FPGA reads the data and compare DNA to produce a comparison result signal output. Xilinx DNA.ppt comes with instructions and commissioning notes.)

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

APB是专为低带宽控制访问，就系统的外围设备例如寄存器接口。这种总线具有一个地址和数据相类似的AHB，但大大减少，低复杂度的信号列表中（例如，没有脉冲串）。它支持32位和66 MHz的信号。 APB主机和从机

基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。(FPGA-based local bus interface. Based fifo contains two programs and the general register.)

VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

出租车vhdl程序，并带有testbench仿真程序，通过开始按键复位，然后根据行使信号进行公里计数，起步价3公里8元钱，超过3公里一公里1元钱(Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometers one kilometer dollar.)

关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom