第六部分 锁相环PLL例程

AVIAddXSubs是一个简单易用的免费程序，用于转换原始srt文件的字幕视频。如果您的硬件播放机无法直接从srt显示字幕，或者即使这样做，结果也不令人满意，那么它的服务将非常有用。使用AVIAddXSubs并转换srt，您可以使用多种选项来配置有关字体、字体大小的字幕；

ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)

数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

北斗定位系统卫星下行信号的基带处理部分——基于FPGA的的直接序列扩频发射机的设计与仿真。，已通过测试。 (Beidou positioning system satellite downlink signal baseband part- based on the design and simulation of the FPGA direct sequence spread spectrum transmitter. , Has been tested.)

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

Fonts for LCD 162x64 (6x8)

Token Bucket Filter queue.

ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)

此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)

对三相电压型逆变器的数学模型进行了详细的数学推导，简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)