它的译码器的VHDL程序

采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)

24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

说明：  适合入门及进阶的100个VHDL练习题，从易到难(100 VHDL exercises for beginners and advanced students, from easy to difficult)

设计一个可容纳四组参赛的数字式抢答器，每组设一个按钮供抢答使用。抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用；设置一个主持人“复位”按钮，主持人复位后，开始抢答，第一答对一次加1分，答错一次减1分

详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)

VHDL CODE FOR SQUARE WAVE GENERATOR

RS编码器的fpga实现，有TESTBench(RS encoder to achieve the fpga, and TESTBench)

说明：  fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

this a test keyboard code -this is a test keyboard code