它的译码器的VHDL程序

这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)

我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)

it is a matrix library. it is needed for fir fier.

说明：  vhdl常见小实验代码，包括二进制比较器，4选1,8421十进制，8421转化成格雷码，8421余三码，分频器，数据码译码器，二进制减计数器，四位环形计数器等(VHDL common small experiment code)

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)

基于vhdl的dds任意函数发生器的实现和仿真

说明：  Implementation of CORDIC atan block in VHDL

quartus工具入门文档，altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.

适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.

EV10AQ190A配置程序 EV10AQ190A configuration program(EV10AQ190A configuration program)