基于Avalon总线的PWM的实现，verlog语言编程

基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6)

图片采用3x3均值滤波，用Verilog语言描述，输入输出分别使用外同步(Pictures are filtered with 3x3 mean and described in Verilog language. Input and output are synchronized with each other.)

数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)

led大显示屏发送卡代码，非常珍贵的，大家多多下载，和CODEFORGE网站共同发展，谢谢这个网站，这么多资源，对软件工程师真的是非常有用，再次感谢

说明：  基于FPGA的任意波形发生器DDS,verilog编写，正常使用(Arbitrary waveform generator DDS based on FPGA)

vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

matlab仿真2ask和4ask.可观察信号的时域波形和频谱图。(Matlab simulation 2ask and 4ask. Can observe the signal time domain waveform and spectrum.)

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)