ripple carry adder

基于fpga的spi  master  testbench，             适合初学者

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

to learn bout development of vhdl code

基于Nios II checksum利用 altera的验证C2H accelerator的系统，已用DE-2 board 验证过， 里面还有DMA 方式的 component，Software Code, Custom Instruction, 和普通的component 各做了比较。 对想了解NiosII 系统的应该有很大的帮助。

利用Verilog编写的 小程序源码及测试,包括流水灯，交通灯 ，等小程序。

超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)