Verilog 小程序源码及测试

基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)

一个简单的UART串口程序，能实现数据的发送与接收，但没有奇偶校验等验证数据传输是否正确。(A simple UART serial program, can send and receive data, but there is no parity and other validation data is correct.)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

AMBA_APB verilog code

Control Unit VHDL code. Xilinx Spartan 3E board

说明：  LTE is an abbreviation for Long Term Evolution.

这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)

说明：  半带滤波器，工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

首先根据连续运算的过程，用状态机做出键盘输入模块，然后根据原码补码的特点做出加、减、与、或、比较运算的8位ALU，之后做出将16位二进制数显示出来的显示模块，再根据连续运算流程并考虑与键盘输入的配合，做出了音乐计算器最核心的控制模块，完成输入数字的存储、运算、显示功能，最后加入音乐模块，实现全部功能。