是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间...

verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)

RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)

making a simple clock using altera vhdl

Verilog for SPI Core source code

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

A simple Manchester Encoder to convert serial data to Manchester encoded data.

verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency

说明：  altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)