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pipelined_fft_256
verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)
- 2017-06-28 21:56:53下载
- 积分:1
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rs-codec-8-16
RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分:1
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making a simple clock using altera vhdl
making a simple clock using altera vhdl
- 2022-04-16 21:53:47下载
- 积分:1
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SPI的核心源代码,verilog
Verilog for SPI Core source code
- 2022-01-25 20:51:31下载
- 积分:1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分:1
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MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子,生成的是一个定点的正弦数据表文件,需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分:1
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一个简单的曼彻斯特编码器,将串行数据转换为曼彻斯特编码数据。
A simple Manchester Encoder to convert serial data to Manchester encoded data.
- 2022-06-20 14:27:09下载
- 积分:1
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verilog prescaler for the realization of the odd
verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency
- 2022-08-08 15:56:02下载
- 积分:1
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Verilog_Ip_RAM
说明: altera ram ip教程。对RAM进行读写操作,写32个数据到RAM中,再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)
- 2020-08-17 11:38:21下载
- 积分:1
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Xilinx-Timing
Xilinx FPGA 时序约束资料,原厂出品,经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分:1