华为 典型verilog 程序设计 大全

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)

实现方法大同小异，这个亲测仿真无误,内含有全部quartursII文件

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers

关于FPGA排序算法的研究文献，有全排序和一些归并算法的文献介绍。(FPGA sequencing algorithm on the literature, there are some sort of sorting algorithm and the literature on the merger.)

基于ARM_FPGA的嵌入式数控装置研究，有具体的方案，思路，程序(ARM_FPGA based embedded CNC device research, there are specific programs, ideas, procedures)

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

Termometric 代码 DAC 的 14 位到 76 位 Verilog 语言。源 decoder.v 和 decoderTB.v