组合电路的设计8位加法器设计(ADD8.vhd)

4-Bit BCD Adder in Verilog

一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.

1024点fft verilog hdl(1024-point fft verilog hdl)

包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))

Description of a sistolic arhictecture for a FFT implementation in FPGA.

除法器-Divider

将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)

基于FPGA 的VGA波形显示，dds产生三角波正弦波(Vga waveform display based on FPGA, using DDS to generate sinusoidal triangular wave)

LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device