组合电路的设计8位加法器设计(ADD8.vhd)

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

An odd parity checker as an FSM using VHDL

8051核的vhdl原代码。-8051 core VHDL source code.

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

papers based on distributed arithmetic.

基于FPGA的画中画处理PDF技术文档，采用SD卡里图片读出来做为底图，然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation )

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler

该代码实现了对SD 卡的读写操作，是一个较好的范例。(The code achieves access reading SD CARD based on DE-2，It is a good example。)

这是我们eda的课程大作业，用quartus仿真循环彩灯并下到板子里能完美的运行出四种波形。工程比较完整，希望对大家有帮助。