组合电路的设计8位加法器设计(ADD8.vhd)

verilog延时电路的不同写法，和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)

wishbone 源代码，opencore-wishbone source code, opencore

调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)

说明：  关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)

&单元格

青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err

3-8译码器地简单实现，采用QUARTUSii5.0环境编译-3-8 decoder to realize a simple, using the compiler QUARTUSii5.0 environment

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)