视频编解码lamda计算

基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)

使用CycloneIV芯片，实现对高精度ADCad9226的数据采集。内有详细代码说明，并附有调试结果(Use CycloneIV, to achieve high-precision data acquisition ADCad9226. Along with debugging results)

hdlc协议的封装与解析，fsc校验，完整的例程代码(Decode and Encode an HDLC packet ，using FCS16 calculation)

这是一个关于的RTL时钟门控技术LECG此源代码是在门控时钟的应用LECG技术

SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)

Implementation of Serial Infrared decoder for low-speed IrDA communications.

vhdl program of matlab file converted to vhdl

实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)