FPGA NIOS II W5500

实现任意整数倍的信号分频，可调，不存在毛刺，波形完整，可运于信号的分析与检测(Arbitrary integer multiple of the signal frequency, adjustable, there is no glitch, waveform integrity, and can transport the analysis and the detection signal)

实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

decoder 2-4 digital core

基于Verilog的串口通信源码 ，实现串口通信功能(Verilog source code based on serial communication)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

采用延时锁相环设计时钟延时电路，然后通过比较时钟信号来判断时钟信号是否发生时毛刺。压缩文件是一个VIVADO2015.1写的工程，包括测试文件，verilog语言编写

说明：  CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。 本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)