Booth乘法器

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)

FFT implementation using C program

最近组长给分配的任务，这几天一直在做，比较郁闷的是用的器件是XC400XL系列的，只有ISE4.1支持，用惯了7.1i的我还是要适应一阵子（关键4.1是一个试用版的）。挺折腾的，不说了，放上顶层模块：-。。。

用FPGA实现SDRAM的操作，具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note

简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

have a good documenty

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)

huawei代码编码规范，包含基本的verilog的语法等编码规范，业界经典(Huawei code coding specification, including the basic syntax of the Verilog code, the industry classic)

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University