Booth乘法器

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

Vhdl Golden Reference Guide.pdf

代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )

it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates

DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under

联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)

这是用verilog硬件描述语言编的5分频代码-This is verilog hardware description language code is compiled by five divider

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

matlab bpsk with rayleigh performance expirement

PS2 Module for Altera DE2