XILINX FPGA on internal training materials in Chinese

VHDL实现的超前进位加法器-the VHDL-ahead Adder

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

说明：  Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)

8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

一些非常有用的程序，均经过调试，让大家一块共享。(Some very useful procedure, have been testing, so that everyone shared one.)

关于FPGA的一些例程，包括CORDIC数字计算机的设计，RS(204,188)译码器的设计等。(Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc.)

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative

该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)