EDA设计数字频率计

实现基于NIOS的 EP3C16与加速度传感器NMA7455的IIC基本通信(Realization of based on NIOS EP3C16 and acceleration sensor NMA7455 IIC of basic communication )

这是Verilog代码使用Verilog实现交叉。

对数计算源程序，能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)

fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

VHDL的基本语法，应用，建模，编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)

实现快速傅里叶变化基-2下的256点DIT-FFT(The 256 point didit -FFT is implemented in the fast Fourier transform base -2.)

说明：  基于BP算法的LDPC译码程序，采用vhdl语言，bp算法(BP algorithm based on LDPC decoding program using vhdl language, bp algorithm)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

光滑的乘法 ；算法是 ；乘法 ；算法，将两个带符号的二进制数的补码表示法。该算法是由安得烈唐纳德发明的展位 ； ；1950在伯克贝克学院在布卢姆斯伯里研究晶体学，伦敦