展位乘数

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

关于VHDL和verilog的数码管显示程序，写的很好，值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)

vhdl测试程序，用于初雪者熟悉hdl的具体语法应用。比较简单了。(VHDL test procedure for the First Snow hdl who are familiar with the application of specific syntax. A relatively simple.)

用fpga实现SDI（ xapp1014-xilinx-sdi）赛灵思原厂资料(Using fpga implementation SDI (xapp1014-xilinx-sdi) Xilinx original data)

32位单周期校验码

this project is about FIR FIlter By VHdl codes in the ISE.

Verilog代码为Sigma-Delta ADC的实现。Verilog是包含testbench。NDIFF V。V的冬天。readmem V。V梳状滤波器。combfilter_tb V。combfilter_wrap.vhd

说明：  这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)