异步FIFO的verilog代码

FPGA控制DM9000A进行以太网数据收发的Verilog实现, 详细描述了DM9000A网络接口芯片的功能，对于DE2开发板上的学习很有帮助。还上载了C程序的实现以及Verilog 代码的实现，

verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)

uartuartuartuartuartuartuart 基于安排不

led 发送卡代码(led send card verilog)

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)

FPGA实现LC12S无线通讯模块收发，使用Verilog语言。程序实现一个模块根据案件发送数据，另一个模块接受导数据后点亮LED灯。程序在XC3S500E上实现。

实现FPGA接收429板卡发送的信号，并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)