与非门的 rtl 代码

本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)

FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

verilog程序仿真滤波器 16阶 运用加法器和乘法器 40KHZ 16位并入并出

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)

设计一个8位的简易频率计，测出信号的频率，即1s内变化的次数。(An 8-bit simple frequency meter is designed to measure the frequency of the signal, i.e. the number of changes in one second.)

描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

这个是verilog下miller米勒编解码，小实验。直接运行即可，将时间轴拉大即可看到具体波形。

说明：  LDPC的编解码的实现，适合初学者学习，大家可以多交流(The implementation of LDPC Encoding and decoding is suitable for beginners to learn)