verilog滤波器仿真

VHDL Coding style guide

SPI协议的VHDL/Verilog语言实现。(SPI agreement VHDL/Verilog language.)

24位x24位的乘法器 十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)

多件键盘键值向上位机串口输出，接受并执行上位机串口的控制，串口使用ASCII码传输，串口逻辑控制逻辑按键去抖均采用Verilog实现。读此代码可以理解串口收发逻辑、键盘去抖、串口控制逻辑，相信对业内人士有所帮助，内附ASCII与HEX换算表

verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

have a good documenty

用verilog hdl编写的248分频器,有助于对verilog编程语言的了解，可直接用于FPGA编程

利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)

这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)