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verilog写sober边缘检测
之前看到很多人用fpga写边缘检测,都是调用了fpga的ip,这里我把这写ip都用verilog写出来,用asic实现sober边缘检测。
- 2022-02-27 08:55:54下载
- 积分:1
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TCD1254FGF_Drive
基于FPGA Verilog驱动线性TCD1254GFG传感器驱动程序,驱动频率2MHz,帧率333帧每秒,曝光时间调节范围0-3000us,带数据读取时序1MHz。(The driver of linear TCD1254GFG sensor is driven by Verilog based on FPGA. The driving frequency is 2MHz, the frame rate is 333 frames per second, the exposure time adjusting range is 0-3000us, and the reading time sequence is 1MHz.)
- 2018-08-25 11:19:53下载
- 积分:1
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1024point-fft--using-verilog-hdl
1024点快速傅里叶变换,使用verilog hdl硬件描述语言(1024point FFT,using verilog hdl)
- 2013-03-09 10:54:42下载
- 积分:1
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1151175
Image Embedded VHDL Code by using watermarking technique
- 2013-03-14 16:53:07下载
- 积分:1
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tpc_decode_vhdl
基于VHDL的TPC译码器的设计,简述了tpc译码的算法步骤,tpc硬件实现的模块和部分vhdl程序(TPC decoder VHDL-based design, outlines the decoding algorithm steps tpc, tpc hardware modules and some vhdl program)
- 2020-11-20 10:59:37下载
- 积分:1
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PIP
基于FPGA的画中画处理PDF技术文档,采用SD卡里图片读出来做为底图,然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation
)
- 2014-07-10 17:56:04下载
- 积分:1
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整个工程代码
说明: 掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序,熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分:1
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esvl
MATLAB Filter Design HDL Coder
Simunlink HDL Coder
Xilinx ISE Webpack
- 2011-06-15 19:56:11下载
- 积分:1
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Character_LCD
This Book description about LCD in Board DE2
- 2012-07-06 11:28:58下载
- 积分:1
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ste_svpwm
实用Verilog编写的SVPWM程序,产生出SVPWM波形,可用于实现同步电机或者异步电机的空间矢量控制算法。(Practical Verilog of SVPWM written procedures, resulting in the SVPWM waveform can be used to implement the space vector control algorithm of the synchronous motor or induction motor.)
- 2021-04-18 16:58:52下载
- 积分:1