verilog下miller米勒编解码

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能(Verilog HDL language (15,7,2) BCH encoding and decoding functions)

以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

通过随机数产生原理进行verilog编程，从而实现FPGA的随机数产生(Through random number generation principle for Verilog programming, so as to achieve the FPGA random number generation)

Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

一个9层电梯的代码。每层电梯入口处，要求开关1，电梯内设有乘客到达的停止开关的水平。（没有下降的按钮，一楼九楼没有上行键）

用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)

在fpga中对GPS信息采集程序。具有很好的参考性(In the fpga in the GPS information collection procedures. Has a very good reference)

AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)