信号完整性，设计FPGA的基础

基于CPLD器件的线型CCD东芝TCD1501的驱动程序，用verilog语言开发。(CPLD devices based on linear CCD driver Toshiba TCD1501 using Verilog language development.)

matlab file for image contrast..

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

实现一个简单的电子钟，其时间（时，分，秒）可以设置和更改，设置和更改的同时不会影响其他显示的变化（相互独立）。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2

Watch Dog Counter reset the output when the given timing meets.

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

a sequence generator