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Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)

说明：  Matlab - to hdl code for square root

fifo的代码,经过测试可以使用，很有用处，可以放心使用(a fifo module,the code has been tested and it is usefull)

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

关于verilog的知识点和关键点的总结(Summary of knowledge points and key points of Verilog)

SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion

此程序描述了数字电路中与门的逻辑功能。所采取的硬件描述语言为VHDL。程序结构采用了dataflow的写法。请大家仔细阅读。本程序已通过了Altera quartus的验证。确保准确无误。

详细介绍了VHDL的28个程序。从简单到复杂。介绍详细-Details of the 28 procedures VHDL. From simple to complex. Detailed introduction