assign LEDs to Siwitches on altera fpga

ram 的ahb接口，ram ahb interface 好用的中转接口ram 的ahb(ram ahb interface ram ahb interface ram ahb interface)

4 bit convoltion with vhdl.

雷达基本恒虚警处理，CA-CFAR(单元平均恒虚警处理),OS-CFAR（有序类恒虚警处理）,SO-CFAR（选小类恒虚警处理），(radar basic constant alarm operation,obtaining os-cfar,so-cfar,os-cfar,ca-cfar)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

AD706在Sparten6使用的FPGA代码，测试通过(AD706 FPGA Code In Sparten6)

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

说明：  spartan6学习资料，官方资料，用户手册，包括5个主要文件(Spartan 6 Learning Materials, Official Materials)

USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)