AHB 仲裁

基于FPGA控制的AD9854DDS任意信号发生，实现了宽带线性调频信号等多种调制信号已经单频信号

LDPC COded OFDM System

Meyers wavelet. DWT VHDL.

800x600@60Hz VGA 时序产生的 Verilog 此外包括一个软件二 13.0 测试项目。在 Altera DE0 开发板执行测试。

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

说明：  This is code of UVM CALLBACK function.

基于MIPS指令集的32位CPU设计与Verilog语言实现的单周期CPU，内含源代码和实验设计报告及实验仿真截图，与大家共享~

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)