A counter that starts from 0 and increments mod 16 on each rising edge of the cl...

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples

SOPC系统的I2C代码 直接可用，可作为ＩＰ核用到自己的系统中(SOPC system I2C code directly available, can be used as an IP core in your system)

wiley2007年的新书高级FPGA设计作者是权威的设计咨询公司老总，经验之谈-wiley2007-year senior FPGA design book author is the authority of the design consulting firm CEOs, experiences

一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.

TFT 液晶屏显示，通过按键，显示不同的曲线(TFT LCD display)

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)

FPGA连接PCI9504的电路图。以及PCB文件(FPGA connected to the circuit diagram of the PCI9504. And PCB files)