A counter that starts from 0 and increments mod 16 on each rising edge of the cl...

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code

Counter written in VHDL.

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

说明：  1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT

making a simple clock using altera vhdl

Arbiter code for simulation purpose

说明：  basic verilog code on siso, piso, sipo

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

VHDL examples for 16x16 times, if need detail pls let me know

4 seg display, button debouncer, and controller for parking meter