A counter that starts from 0 and increments mod 16 on each rising edge of the cl...

此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)

基于 CPU 的精确计时器，时钟频率越高，计时越准(Based on the exact CPU timer, the higher clock frequency, the more time-quasi-)

此模块模拟alu（算术逻辑单元）和测试台，以验证其工作是否正确。

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

本文详细介绍了我们的电气工程项目；

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.-Used VerilogHDL to make a frequency builder.

里面是VHDL的一些例子，大家可以看一下，蛮不错的，对大家提高VHDL水平很好的.-There is some examples of VHDL, we can look pretty good on the U.S. improve the level VHDL good.

Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现-Hynix" s 8M Byte SDR SDRAM Simulation of the Verilog language

VHDL programming by example