登录
首页 » Verilog » uart code dsdlab with my clock code

uart code dsdlab with my clock code

于 2022-09-14 发布 文件大小:211.45 kB
0 174
下载积分: 2 下载次数: 1

代码说明:

uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • ug_dsp_builder
    本文是Altera公司编写的dspbuilder的设计方法,但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
    2008-12-14 01:33:58下载
    积分:1
  • LZ77_1
    Package include hardware implementation of Lz77 algorithm
    2021-04-26 10:38:45下载
    积分:1
  • 系统设计
    基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)
    2020-06-21 02:00:01下载
    积分:1
  • Verilog Booth 型乘法器
    此文件描述的 verilog booth 型乘法器的代码。源代码是模拟和验证效果会更好
    2022-08-21 23:35:26下载
    积分:1
  • vhdl_course_tw_CIC
    台湾IC中心VHDL讲义,内容详细,适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)
    2011-01-10 19:06:38下载
    积分:1
  • FFT_16
    FFT快速傅立叶变换-verilog,基于verilog的FFT源码,QuartusII上仿真通过(FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation)
    2020-09-08 20:28:02下载
    积分:1
  • 单相逆变simulink仿真
    说明:  利用Matlab/simulink实现电力仿真,其中单相逆变可用于多电平变流器的基础使用,本案例提供了不同调制手段实现逆变的模型(Matlab / Simulink is used to realize power simulation, in which single-phase inverter can be used as the basis of multi-level converter. This case provides the inverter model with different modulation means)
    2019-11-12 15:03:55下载
    积分:1
  • cordic
    基于VHDL语言编写,可下载到FPGA板子上实现的cordic算法实现的设计,并用该算法实现sin和cos的计算,计算结果显示在数码显示管上,已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)
    2013-03-21 16:52:41下载
    积分:1
  • CAN
    说明:  ZYNQ中 PS 端 CAN接口的基本使用方法,并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
    2020-04-03 16:41:52下载
    积分:1
  • NiosII_mycpu
    基于NiosII 的SOC FPGA验证系统,适用初学者学习Altra Quartus II软件,以及C语言 veriog,以及MCU调试流程
    2022-03-19 06:31:20下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载