FPGA实现LC12S无线通讯模块收发

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

说明：  VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。(VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.)

VHDL 的100例程代码，能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)

this program does something im not sure what but all i want is to get into the damn site thank you

应用背景大多数Zedboard平台创造巨大的项目为示范能力Zedboard。本设计实现了全合成，证明目标Zedboard工作。它集锦GPIO模块和所有的默认命名的单主机双奴隶配置的AXI总线的公约。实例化一块Xilinx互连标准复位块。关键技术新的FPGA的发展发生所有的时间。本设计的基准电流软件Xilinx和Vivado工具自动化。Tcl脚本是不包括在内，用户精通当前工具能够从源中提取数据流。在赛灵思WebPACK创建的项目，而是一个开端的用户可以在伊拉降看信号发送到GPIO块学习互连IP

xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)

本代码是cache代码，采用最近最少使用算法。代码量大约1000-2000行，程序包括cache替换算法的实现。映像规则的选择，以及全部的仿真程序。

开关电源中用单片机产生可调电压控制PWM波程序,ADC0832读取输出电压(Single-chip switching power supply using adjustable voltage control PWM wave generation process, ADC0832 read the output voltage)

FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)