101序列检测器

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)

里面有状态机的应用，比如在HEAD那个状态，统计5个0x55d5数，那么 如何知道现在希望是55还是d5呢？ 假设head_flag信号，若head_flag=0，希望是55；若是head_flag=1，希望是d5。 4. 初值：0；加

verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)

说明：  Basic principle of LDPC code and FPGA implementation of LDPC code

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

uboot i2c driver code for arm a5 dual core cpu imapx820, which is an soc of infotmic.

说明：  难得的soc设计用的ddr3 verilog，可用于学习！！！！！有datasheet ，可仿真(soc ddr3 verilog for study !!)

频率除以 3 的计数器。用于筛选器图形。所需的频率获取除以 3。

用于检测100MHZ频率，带51单片机软核，控制外部液晶显示器以及按键等(Used to detect 100MHZ frequency, with 51 SCM soft core, control of external LCD monitors and buttons, etc.)