乘法器功能 直接实现两个数字信号的相乘～

用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0； -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0

本程序利用VHDL实现二维离散余弦变换，经本人测试，在Quartus II7.0软件上可正确仿真，希望大家积极采纳

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

useful VHDL document for programmer

说明：  发送两个频段的脉冲 个数和频率均可调 发送两个频段的脉冲 个数和频率均可调(pluse and adjust the width of pluse pluse and adjust the width of pluse )

Code to controlling a Image sensor - CMOS(Code to controlling a Image sensor- CMOS)

OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)

verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)