GPIO的RTL代码

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

说明：  XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)

在交通灯系统中（图1）,路口A、B、C、D均需要红、黄、绿、左转四盏灯(用RYGL分别表示) ,并且每个路口都需要一个倒数的计时器,假设绿灯每次维持的时间是45 s ,在亮绿灯的最后5s亮黄灯5s作为提示 ,左转灯15s，在亮左转灯的最后5s亮黄灯5 s作为提示 ，红灯60s。交通灯系统大多是自动控来指挥交通的,但有时需要由交警手动控制红绿灯,所以要求设计的该交通信号系统需要具有该功能。

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

Token Bucket Filter queue.

4位密码锁，可设置密码，三次密码错误后，锁死，密码错误报警，密码错误红灯亮，密码正确绿灯亮，基于FPGA实现，Cyclone II  EP2C35F672C6 仅供参考

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

基于fpga的物理不可克隆函数（PUF）模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)