GPIO的RTL代码

说明：  此程序为调试通过的程序，带有I2C总线功能的程序.(this procedure through the debugging process, with I2C bus function procedures.)

ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)

用Verilog实现的16位进位先行加法器。实现了饱和算法。

6位密码锁，密码锁控制器是硬件与软件的结合。根据设计要求，决定以FPGA芯片和VHDL语言设计此电子密码锁(6 locks, the lock controller is a combination of hardware and software. According to design requirements, the decision to the FPGA chip and VHDL design electronic locks)

基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

说明：  基于FPGA的USB接口设计，实现了USB与FPGA的通信(USB interface to FPGA-based design, implementation of the USB communication with the FPGA)

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果(described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output)

VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)