Verilog实现的gardner算法

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

ALTERA FPGA CLPD

CSCC标准下的RS(255,223)码的译码器设计，采用verilog语言编程实现，在软件QUARTUS II 9.0环境下仿真通过，并在CYCLONE IV系列开发板调试通过。

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

PRBS的验证就是PRBS的产生的反过程，具体方法是Transceiver接收端首先将收到的数据寄存一拍（并行 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures )

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)