Verilog实现的gardner算法

FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)

数字脉冲检测序列的前端设计，利用verilog硬件描述语言进行功能设计，利用modelsim软件进行功能仿真，根据测试代码进行检测与计算，看仿真波形是否符合功能设计，在进行FPGA下载，在实验开发板上实现功能输出，完成设计。

用VHDL编写的曼切斯特编解码，适用于以太网上流行的基带传输数字编码。(Manchester encoding and decoding written using VHDL, popular Ethernet baseband transmission of digital coding.)

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)

LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)

Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.

这个课程设计的题目是模拟电压采集电路路与程序设计,报告书的内容都比较详细. (The topics of this course design is an analog voltage acquisition circuit Road and program design, the contents of the report are more detailed.)

说明：  OFDM载波同步，Verilog编写，完全正确！！！(verilog )