prbs编码FPGA实现

今天的系统芯片 （SoC） 验证发生在低的抽象级别，通常在寄存器传输级(RTL)。随着 SoC 设计的复杂性，它是越来越重要了，搬到较高抽象级别的验证。硬件/软件协同仿真是这一步方向，而是由于错误的处理器不足够型号和低速的硬件仿真速度。系统级监测，通常用于基于事件的软件调试，提供有关任务调度事件，任务间通信信息和， 同步信号量/资源、 I/O 中断等我们目前 MAMon1可以监测系统两个监视逻辑级和系统级的 单/多处理器片上系统。小硬件探测器单元集成在 SoC 设计中，并通过一个基于主机的监测工具环境的并行端口链接连接。探头装置在运行时，在目标系统中收集的所有事件和时间戳他们的分辨率为 1 s。事件然后存储在主机上的数据库进行进一步的处理。本文将叙述 MAMon 以及它适用于软件和硬件监控。本文还描

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

FPGA上用verilog写的SPWM控制程序，完美运行！自由调试，毕设内容，十分宝贵(The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable)

基于FPGA实现蜂鸣器播放音乐的功能 使用芯片为EP2C8Q208C8N,使用普通蜂鸣器，由于频率不同可实现放歌功能，本例设计的是《友谊地久天长》，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。(Play music based on FPGA buzzer functions using chip EP2C8Q208C8N, using ordinary buzzer, since the frequency of different functions can be realized sing, in this case the design is " Auld Lang Syne" , using Verilog language programming, this project examples files, simulation, waveform, tested can be used.)

共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)

说明：  verilog实现的fft算法，其中还有ifft算法(FFT algorithm based on Verilog)

说明：  本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。(I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book )

说明：  高速FPGA 开发设计资料，包括全部的设计方案和开发例程，可快速入手FPGA设计。(High speed FPGA development and design data, including all the design schemes and development routines, can quickly start FPGA design.)

运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)

芯片验证漫游指南附赠源代码,适合初学者学习(Chip Verification Walkthrough Guide with Source Code)