CSCC标准下的RS码译码器的FPGA实现

说明：  一本很经典的IC设计中文入门书籍，由任艳颖，王彬编著，翻印几百万册(A very classic introduction to Chinese in IC design book, compiled by Ren Yanying and Wang Bin, reprinted millions of copies)

说明：  网口UDP的FPGA仿真代码，经过测试能够实现预想功能(etherneit udp verilog fpga code)

良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

里面包含了三段代码，主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声，然后计算其数字特征及对这些信号进行频谱分析和功率谱分析，里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)

用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

非常好的verilog书 国际牛人写的 适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)

说明：  一个1MHz的FIR低通滤波器。 ① 时钟信号频率16MHz; ② 输入信号位宽8bits，符号速率16MHz； ③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数； ④ 写出测试仿真程序。(A 1MHz FIR low pass filter. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined. (4) Write the test simulation program.)

个人作业，mips流水线cpu，支持mips-c3指令集

说明：  FPGA实现基带成型滤波器，升余弦滚降系数，多进制调制(FPGA)

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)