CSCC标准下的RS码译码器的FPGA实现

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

is61lv25616简单的verilog程序，完成sram读写(is61lv25616 simple verilog program, complete sram read and write)

积分器的一种实现方法：每级积分器都是一个反馈系数为1的单极点IIR滤波器, 其传递函数为:(An implementation of an integrator: each stage integrator is a single pole IIR filter with a feedback factor of 1:)

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

VHDL code for MC68000

串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。(uart communication)

ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)

利用stm32F407实现的等精度测频，可以精确测量频率，误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)