数码管显示程序，可以显示当前的数值，可以动态显示和静态显示 可以选择显示方式...

QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)

AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)

this is a verilog code for root raised cosine filter

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II，QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-

此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA

出租车自动计费系统，功能完善，方便快捷，十分好用-taxi