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bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
- 2023-01-08 07:50:03下载
- 积分：1
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80211_Transmitter_VerilogHDL
802.11a Transmitter implementation Using Verilog
- 2021-01-20 15:28:41下载
- 积分：1
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直接数字合成器，可以直接输出所需的波形
直接数字频率合成，可以直接输出所需要的波形-Direct digital synthesizer, you can direct output of the waveform required
- 2022-01-28 03:58:57下载
- 积分：1
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08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008
08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl
- 2022-03-29 09:41:25下载
- 积分：1
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tcp_tiaoshi
fpga_sopc_enc28j60_tcp_ip_测试，源码程序包，本人测试通过！(Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!)
- 2012-03-05 11:26:19下载
- 积分：1
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jiaotongdeng
交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)
- 2013-08-25 10:02:34下载
- 积分：1
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This is a simple routine FPGA is mainly based on FPGA
这是一个FPGA的简单例程，主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
- 2022-03-06 20:54:43下载
- 积分：1
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zixiechengxu
用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
- 2021-04-18 15:28:51下载
- 积分：1
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fpga
verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)
- 2017-07-27 20:05:25下载
- 积分：1
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DDR3
spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)
- 2021-01-07 08:48:52下载
- 积分：1
