VHDL的循环冗余校验发生器和接收器

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

说明：  ZYNQ中 PS 端 CAN接口的基本使用方法，并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)

自己编写的，浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)

这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.(This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.)

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码(NAND Flash control access and control of the synchronous FIFO verilog code)