VHDL的循环冗余校验发生器和接收器

基于FPGA的乐曲发生器电路设计 附含源代码（quartersii环境下运行）-FPGA-based circuit design of the music generator containing the source code is attached (quartersii environment to run)

说明：  可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)

使用Verilog编写的正弦波生成工程，使用ROM核产生，利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)

adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

基于PID 控制算法的直流电机控制，输出PWM波，很容易用(motor control)

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client