按键消抖，矩阵键盘

Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)

ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)

VHDL Design of BCD to 7-segment decoder using PROM

UART 的接收跟发送 verilog写的 时序跟功能仿真也写在了里面

vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

本文阐述了设计的 4 位携带看前方 adder.this 加法器是比较会波及进位加法器的高速度。

测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

说明：  基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者……(ＤＤＳ　based on Verilog ＤＨＬ for FPGA　)

说明：  设计一个哈夫曼编码器 要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。 ① 组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。 ② 输入数据序列的长度为256。 ③ 先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Designing a Huffman Encoder Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element. (1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001. (2) The length of the input data sequence is 256. (3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence.)