按键消抖，矩阵键盘

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

sdram_cmd.v是控制sdram的命令集合。网上资料，是控制sdram的命令集合。网上资料。控制sdram的命令集合。网上资料控制sdram的命令集合。网上资料。

基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现(FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve)

sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能(SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state)

Code VHDL for control VGA FPGA: Xilinx, Altera

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)