用VHDL实现的DDS逻辑，大家可以参考下

verilog program for 8-bit multiplier

重点介绍了双线性插值算法和该方法的Ｆ Ｐ ＧＡ硬件实现 方法， 包括图像数据缓冲单元、 插值系数生成单元以及插值计算单元等。(Highlights the bilinear interpolation algorithm and the method of F P GA hardware The method includes an image data buffer unit, the interpolation coefficient generating unit and an interpolation computing unit and the like.)

这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new design

rc6 algorithm designed based on verilog and is verified

Verilog for SPI Core source code

最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))