can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do wit...

数字电子钟设计完整设计，包括原理介绍，程序设计，波形仿真-Design a complete digital electronic clock design, including the principle of introduction, program design, waveform simulation

PrimeTime Intro to STA -PrimeTime Intro to STA

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

乒乓球游戏，用led灯控制水上乒乓球，选择了控制键进行操作。详细信息请参见自述

实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

采用VHDL语言编写，此题为全国大学生电子设计竞赛题目，产生一个伪随机信号，并用时钟提取模块提取时钟，最终能在示波器上获得眼图，验证实验结果。此程序已经经过本人亲自验证，完全可用，可用于电赛培训之中。

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)