AD转换

韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验(Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and keystrokes 4 experimental statistics)

一个9层电梯的代码。每层电梯入口处，要求开关1，电梯内设有乘客到达的停止开关的水平。（没有下降的按钮，一楼九楼没有上行键）

statemachine project for my school

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

本程序是在AWGN下的LDPC码的仿真程序，本程序优点是译码效率高，速率很快，可以仿帧数很大的图。(the decoder for LDPC under the AWGN channel)

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )

DE2_115_TV开发板例程，含SDRAM及异步FIFO应用: 通过协调器控制2入2出共4个FIFO操作SDRAM

FPGA做机器人舵机控制系统，verilog(FPGA to do the robot servo control system, verilog)