8路彩灯变换

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

在以太网通信中，连接MAC与物理层需要使用MII接口，此程序提供了MII接口的详细设计。

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

说明：  FPGA实现的AD采样控制程序的源码，欢迎大家下载(FPGA implementation of the AD sampling control)

OMAP5912 UART的测试程序 包括头文件 源文件等。(OMAP5912 UART program test)

interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials are intertwined

Fonts for LCD 162x64 (6x8)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

rc6 algorithm designed based on verilog and is verified