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zhinengchezaishipingxitong
设计了车载视频显示系统,设计了基于FPGA系统结构的车载视频显示电路板,利用FPGA显示视频控制,采集通道时许控制等。(The on-board video display system design, design the system structure based on FPGA video shows the circuit board, using the FPGA show video control, acquisition channel make control, etc
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- 2011-12-08 15:37:21下载
- 积分:1
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AN66806
提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)
- 2013-08-13 14:42:55下载
- 积分:1
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30
说明: 30 bus for atp design
- 2016-02-14 19:41:55下载
- 积分:1
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74LS
数字逻辑与系统的关于所有的器件74LS的介绍,功能表(Digital Logic and System devices 74LS on the introduction of all the menu)
- 2010-12-30 17:27:19下载
- 积分:1
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circuit_timing
verilog延时电路的不同写法,和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)
- 2014-05-14 18:02:44下载
- 积分:1
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SeggerEval_LPC2478
emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)
- 2012-08-04 13:54:29下载
- 积分:1
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cnv_enc_modify
卷积码(2,1,7)编码器,一个输入,两个输出(Convolution code (2,1,7) encoder, an input and two outputs)
- 2015-05-20 10:21:56下载
- 积分:1
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小灯测试代码
使用Verilog语言编写小灯测试代码,能实现流水灯的功能,代码简单易懂,很适合初学者学习和验证。
- 2022-02-28 22:00:42下载
- 积分:1
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ISE_uart
自己在ISE下用VHDL写的UART,简单,易懂(in ISE using VHDL was the UART, simple, understandable)
- 2021-03-08 21:59:28下载
- 积分:1
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三角函数的Verilog HDL语言实现
以Actel FPGA作为控制核心,通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波,利用Verilog HDL语言实现死区时间可调的SPWM全数字算法,并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
- 2017-07-08 20:59:23下载
- 积分:1