浮点数运算的FPGA实现，包括仿真文件。

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

DS18B20温度测量程序 之后用于在LCD显示屏上显示对应的温度(DS18B20 test code)

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.

说明：  电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)

USB3.0开发板资料，采用CYUSB3.0(USB3.0 development board, using CYUSB3.0)

学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.

this code for integrator for 8 bit signal

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

直接序列扩频通信系统： 包含： 信源、扰码、交织、直扩、BPSK调制、解调、相关、解交织、解扰 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报