VHDL的食谱

微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)

使用FPGA透过RS232与PC的作沟通，

verilog coding for butterworth filter with cut off frequency with 500hz

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read

EasyWifiRadar.zip r ok

与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)

用verilog语言实现DCT编解码 附有DCT的说明(Using Verilog language realize DCT codec with a description of DCT)

用verilog 语言实现七人投票表决器(verilog seven voting)

VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.

DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)