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曼彻斯特编解码,是Verilog语言代码,不多介绍了,用途非常广泛了...
曼彻斯特编解码,是Verilog语言代码,不多介绍了,用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
- 2022-04-01 23:58:18下载
- 积分:1
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AD
说明: FPGA实现的AD采样控制程序的源码,欢迎大家下载(FPGA implementation of the AD sampling control)
- 2021-04-14 21:18:55下载
- 积分:1
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sin_wave
在vivado开发环境下,调用ram IP,实现可调频的正弦波信号发生器。(vivado IP signal generator)
- 2020-09-21 23:27:52下载
- 积分:1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分:1
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pps_ketiao_rb2
FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
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fpga-jpeg
包含DCT变换,RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)
- 2013-07-02 14:10:16下载
- 积分:1
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16b20b_Encoder
16b20b encoder and decoder
- 2013-02-04 13:24:46下载
- 积分:1
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用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。...
用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分:1
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20190718
uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分:1
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Single-port-RAM-
单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)
- 2011-08-07 11:27:59下载
- 积分:1