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基于FPGA的JPEG图像压缩芯片设计
基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
- 2022-01-28 02:00:46下载
- 积分:1
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NCO of the VHDL process is the use of nuclear
NCO的VHDL程序,是利用IP核生成的,超好的,快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
- 2022-03-22 15:41:09下载
- 积分:1
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DW_apb_timer
verilog实现计时器timer,可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)
- 2016-04-05 22:37:39下载
- 积分:1
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LED-clock-display
利用单片机控制LED时钟显示,以及闹钟,程序较大,但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分:1
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vhdl_fir
在matlab仿真的基础上,用maxplus2实现等波纹法的程序代码(In matlab simulation, based on the use of such corrugated maxplus2 realize law code)
- 2008-05-21 20:30:35下载
- 积分:1
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FPGA锁相环实验
说明: FPGA锁相环实验:
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
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GF_2_m_域乘法器的快速设计及FPGA实现,对于rs编翼码的理解和设计有帮助...
GF_2_m_域乘法器的快速设计及FPGA实现,对于rs编翼码的理解和设计有帮助-Domain multiplier GF_2_m_ rapid design and FPGA realization for rs wing made the understanding of code and design has helped
- 2022-04-25 05:12:28下载
- 积分:1
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这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着...
这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
- 2022-05-13 15:53:30下载
- 积分:1
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地铁售票系统,基于VHDL,可实现站点设置,站点选择,选择购票数量,找零等一系列功能。...
地铁售票系统,基于VHDL,可实现站点设置,站点选择,选择购票数量,找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.
- 2022-02-16 02:43:18下载
- 积分:1
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完成十余卷积过程,简单方便,能够这样那样这样,sorry
完成十余卷积过程,简单方便,能够这样那样这样,sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry
- 2022-10-31 06:20:03下载
- 积分:1